1. Field of the Invention
The present invention relates to the production of contact structures on a structured surface of a substrate.
2. Description of Related Art
In many fields there are considerable challenges to producing contact structures due to the increasing demands placed on them in terms of quality and size. Especially for semiconductor substrates, problems concerning electrical contact arise due to the strong increase in electronic performance requirements. As the frequency range above 1 GHz is being opened up increasingly for semiconductor applications, the need to optimize the contact of the active components to the RF ground becomes more marked. Hitherto, in Si components, the mass potentials have been bonded from the front of the chips to the ground contacts of the package via bond wires. Such a bond wire has an inductance of typically 0.5 nH, depending on the length. This corresponds to an impedance of 3 Ohm at 1 GHz. An impedance of this magnitude being present in the emitter and/or source path of an RF amplifier circuit greatly reduces the gain available. Gain losses of 10 dB are not unusual. Even though multiple bonds are of assistance to a certain degree, they still do not, in principle, provide a solution.
In GaAs technology, it has therefore been common practice for a long time to lead the source contacts from the back of the semiconductor chip to the front by means of a metallic via. In silicon technology, a number of process related difficulties, in particular the low etching rates of silicon, have prevented an introduction of such substrate via contacts.
An alternative solution would be a flip-chip technology with metal bumps on the contacts. This technology, however, has the disadvantage of a relatively poor heat dissipation. With small components, such as discrete transistors and MMICs (MMIC=monolithic microwave IC), an added disadvantage is that a larger die size of silicon is required because of the bumps, and that, at least up to now, no flip-chip bonding process exists that would even so much as get close to the cycle times of “upright” die-bonding.
It has been known in the art to create vias wherein a reverse-side photolithography process and further reverse-side process steps are required, which is an extremely difficult task to perform on thin wafers. Such a method has been described, for example, in DE 19816245. On the other hand, it is necessary, for a variety of reasons, to thin the silicon wafers typically to about 50–200 μm, so that for this reason and also because of the enormously long process times, a via on thick wafers is of little use.
In addition, U.S. Pat. Nos. 5,618,752 and 5,608,264 contain descriptions of forming an opening in a silicon substrate, wherein the opening is filled with a metal after depositing a barrier metal layer and an oxide layer. In the above-described patent applications and according to the current state of the art, however, it is practically impossible to fully fill Via holes, which have dimensions of a very high aspect ratio of 1:10, to the required depth using conventional metal coating methods. Therefore it is assumed, in the above patent applications, that after the metal deposition effected by sputtering, evaporation or a CVD process, a residual opening remains, which must be filled up with further filling material. The details disclosed in the above patent applications therefore are not sufficient so as to be able to advantageously produce substrate vias. In addition, the above patent applications do not indicate any practical method specifying how the substrate vias may be exposed and connected in a convenient manner from the reverse side once the front side of the wafers has been completed.
It is also known in the art to produce contacts by means of electroplating. Since the introduction of copper metalization into semiconductor technology, processes based on electroplating have been available which are suitable, in principle, for filling very large via openings.
A precondition for electroplating is a conductive layer which is referred to as a seed layer and typically also includes copper. The seed layer is applied by means of PVD (physical vapor deposition) methods. CVD and electroplating techniques are also possible. The copper seed layer is deposited onto a tantalum diffusion barrier and/or tantalum-based diffusion barrier commonly used for this method, wherein, as is known, PVD deposition is used, but other methods are also possible. Other barrier materials, such as CVD-TiN or electroplated barriers may be applied.
For deep vias having a high aspect ratio, typically 1:10, no reliable and sufficient area coverage of the via-opening sidewall and of the via bottom can be achieved using the usual PVD methods. Literature frequently gives descriptions of the use of Cu-CVD methods for producing the Cu seed layer, for example in the following publication: “Wafer Process and Issue of Through Electrodes in Si Wafer Using Cu Damascene for Three Dimensional Chip Stacking”, Masataka Hoshino et al., Superficies y Vacio 13, 1–6, Diciembre 2001, and the publication: “Processing Techniques for 3-FD Integration Techniques”, S. Burkett et al., Superficies y Vacio 13, 1–6, Diciembre 2001. The above-described Cu-CVD methods have been applied for years in research laboratories, but have not been introduced in semiconductor production. In addition, manufacturers of electrolytes have developed electrolytes which permit electrolytic copper deposition on a barrier, which is also known by the name of high-resistance electrolyte.
In summary, it can be stated that the prior art knows of no technique that would enable the creation of contacts on structured surfaces that would meet the requirements placed upon them by modern technologies, and, in particular, by semiconductor technology.